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? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch may 2009 fsa2257 low r on low-voltage dual spdt bi-directional analog switch features maximum 1.15 on resistance (r on ) for 4.5v supply 0.3 maximum r on flatness for +5v supply space-saving micropak? packaging broad v cc operating range: 1.65v to 5.5v fast turn-on / turn-off time break-before-make enable circuitry over-voltage tolerant ttl-compatible control input applications cell phone pda mobile devices description the fsa2257 is a high-performance bi-directional dual single-pole/double-throw (spdt) analog switch. this switch can be configured as either a multiplexer or a de- multiplexer by select pins. the device features ultra-low r on of 1.3 maximum at 4.5v v cc and operates over the wide v cc range of 1.65v to 5.5v. the device is fabri- cated with submicron cmos technology to achieve fast switching speeds and is designed for break-before-make operation. the select inpu t is ttl-level compatible. ordering information for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . figure 1. block diagram part number package number eco status top mark package description packing method fsa2257l10x mac010a rohs ep 10-lead micropak?, 1.6 x 2.1mm 5000 units on tape and reel fsa2257mtcx mtc14 rohs fsa2257 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 2500 units on tape and reel fsa2257mux mua101a rohs fsa 2257 10-lead molded small outline package (msop), jedec mo-187, 3.0mm 4000 units on tape and reel select pin base band voice/bell ring base band processors with melody ring generation 8 loud speaker amp fsa2257 32 earpiece
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 2 connection diagrams figure 2. pin assignments for tssop (top view) fig ure 3. pad assignments for micropak (top view) figure 4. pin assignments for msop (top view) analog symbols figure 5. analog symbols (top through view) truth table pin descriptions 1 2 3 4 5 6 7 1a gnd 1b 0 2a gnd 2b 0 nc 14 13 12 11 10 9 8 1a 9876 1234 5 10 gnd v cc 1s 1b 0 1b 1 2a 2s 2b 0 2b 1 v cc 1s 1b 1 v cc 2s 2b 1 nc 1 2 3 4 5 2b 1 2s v cc 1a 1b 0 2b 0 2a gnd 1s 1b 1 10 9 8 7 6 1a 9 8 7 6 1 2 3 4 5 10 gnd v cc 1s 1b 0 1b 1 2a 2s 2b 0 2b 1 control input(s) function low logic level b 0 connected to a high logic level b 1 connected to a pin names function a, b 0 , b 1 data ports s control input
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 3 absolute maximum ratings stresses exceeding the absolute maximu m ratings may damage the device. the de vice may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. note: 2. the input and output negative voltage ratings may be exceeded if the input and output diode curr ent ratings are observed. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specif ications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 3. unused control inputs must be held high or low. they may not float. symbol parameter min. max. unit v cc supply voltage ?0.5 +6.0 v v sw dc switch voltage (2) ?0.5 v cc +0.5 v v in dc input voltage (2) ?0.5 +6.0 v i ik input diode current ?50 ma switch current 200 peak switch current (p ulsed at 1ms duration, <10% duty cycle) 400 t stg storage temperature range ?65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c esd human body model, jesd22-a114 8000 v charged device model, jesd22-c101 2000 symbol parameter min. max. unit v cc supply voltage 1.65 5.50 v v in control input voltage (3) 0 v cc v v sw switch input voltage 0 v cc v t a operating temperature ? 40 + 85 c
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 4 dc electrical characteristics all typical values are at 25 c unless otherwise specified. notes: 4. on resistance is determined by the voltage drop between a and b pins at the indicated current through the switch. 5. r on = r onmax ? r onmin measured at identical v cc , temperature, and voltage. 6. flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. symbol parameter conditions v cc (v) t a = + 25c t a = ? 40c to + 85c units min. typ. max. min. max. v ih input voltage high 1.8 to 2.7 1.0 v 2.7 to 3.6 2.0 4.5 to 5.5 2.4 v il input voltage low 1.8 to 2.7 0.4 v 2.7 to 3.6 0.6 4.5 to 5.5 0.8 i in control input leakage v in = 0v to v cc 2.7 to 3.6 ? 1.0 1.0 a 4.5 to 5.5 ? 1.0 1.0 i no(off) , i nc(off) off-leakage current of port b 0 and b 1 a = 1v, 4.5v, b 0 or b 1 = 1v, 4.5v 5.5 ?2.0 2.0 ? 20.0 20.0 na i a(on) on leakage current of port a a = 1v, 4.5v, b 0 or b 1 = 1v, 4.5v or floating 5.5 ? 4.0 4.0 ? 40.0 40.0 na r on switch on resistance micropak (4) i out = 100ma, b 0 or b 1 = 1.5v 1.8 4.6 2.7 2.6 4.0 4.3 i out = 100ma, b 0 or b 1 = 3.5v 4.5 0.95 1.15 1.30 switch on resistance msop / tssop (4) i out = 100ma, b 0 or b 1 = 1.5v 2.7 2.8 4.5 i out = 100ma, b 0 or b 1 = 3.5v 4.5 1.5 2.3 r on on resistance matching 5etween channels (4) micropak i out = 100ma, b 0 or b 1 = 3.5v 4.5 0.06 0.12 0.15 on resistance matching between channels (5) msop / tssop i out = 100ma, b 0 or b 1 = 3.5v 4.5 0.7 0.3 r flat(on) on resistance flatness (6) i out = 100ma, b 0 or b 1 = 0v, 0.75v, 1.5v 1.8 3.0 2.7 1.4 i out = 100ma, b 0 or b 1 = 0v, 1v, 2v 4.5 0.2 0.3 0.4 i cc quiescent supply current v in = 0v or v cc , i out = 0v 3.6 0.1 0.5 1.0 a 5.5 0.1 0.5 1.0
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 5 ac electrical characteristics all typical values are at 25 c unless otherwise specified. capacitance symbol parameter conditions v cc (v) t a = + 25 ct a = ? 40 c to + 85 c figure number min. typ. max. min. max. units t on turn-on time b 0 or b 1 = 1.5v, r l = 50 , c l = 35pf 1.8 to 2.7 75 ns figure 6. 2.7 to 3.6 50 60 b 0 or b 1 = 3.0v, r l = 50 , c l = 35pf 4.5 to 5.5 35 40 t off turn-off time b 0 or b 1 = 1.5v, r l = 50 , c l = 35pf 1.8 to 2.7 20 ns figure 6. 2.7 to 3.6 20 30 b 0 or b 1 = 3.0v, r l = 50 , c l = 35pf 4.5 to 5.5 15 20 t bbm break-before- make time b 0 or b 1 = 1.5v, r l = 50 , c l = 35pf 2.7 to 3.6 1 ns figure 7. b 0 or b 1 = 3.0v, r l = 50 , c l = 35pf 4.5 to 5.5 20 1 q charge injection c l = 1.0nf, v gen = 0v, r gen = 0 2.7 to 3.6 20 pc figure 9. 4.5 to 5.5 10 oirr off isolation f = 1mhz, r l = 50 2.7 to 3.6 ?70 db figure 8. 4.5 to 5.5 ?70 xtalk crosstalk f = 1mhz, r l = 50 2.7 to 3.6 ?75 db figure 8. 4.5 to 5.5 ?75 bw ? 3db bandwidth r l = 50 2.7 to 3.6 200 mhz figure 11. 4.5 to 5.5 200 thd total harmonic distortion r l = 600 , v in = 0.5v pp f = 20hz to 20khz 2.7 to 3.6 0.002 % figure 12. 4.5 to 5.5 0.002 symbol parameter conditions v cc (v) t a = + 25 c t a = 40 to + 85 c units figure number min. typ. max. min. max. c in control pin input capacitance f = 1mhz 0.0 3.5 pf figure 10. c off b port off capacitance f = 1mhz 4.5 12.0 pf figure 10. c on a port on capacitance f = 1mhz 4.5 40.0 pf figure 10.
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 6 ac loading and waveforms figure 6. turn-on / turn-off timing figure 7. break-before-make timing figure 8. off isolation and crosstalk t off t r = t f = 2.5ns 0.9 x v out 0.9 x v out r l 50 c l 35pf 50% gnd 3v 0v control input switch output 0 v out v out t on v cc v cc v b b 0 or b 1 c l includes fixture and stray capacitance logic input waveforms inverted for switches that have the opposite logic sense a s s gnd control input control input c l includes fixture and stray capacitance v bn b 0 b 1 a v out 3v 0v t d v cc v cc 0.9 x v out 50% r l 50 c l 35pf v out t r = t f = 2.5ns gnd off-isolation = 20log network analyzer meas ref 0dbm a v out v in v out v in v out v in on-loss = 20log crosstalk = 20log b o b 1 s v cc 10nf 0 or v cc v cc 50 v out v in 50 50 50 50
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 7 ac loading and waveforms (continued) figure 9. charge injection figure 10. on / off capacitance measurement setup figure 11. bandwidth figure 12. harmonic distortion gnd a b 0 or b 1 r gen v gen + s v cc v out v out q = ( v out )(c l ) in in on on off off off off c l control input v out gnd a b 0 or b 1 s v+ 0v or v cc f = 1mhz capacitance meter 10nf gnd a b n v cc s 10nf analyzer signal generator 0dbm logic input 0v or v cc 50 gnd a b n v cc v in s 10nf analyzer signal generator logic input 0v or v cc r l
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 8 physical dimensions figure 13. 10-lead micropak, 1.6 x 2.1mm package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . note: click here for tape and reel specifcations, available at: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf bottom view top view recommended land patter n side view 2x 2x notes: a. package conforms to jedec registration m o -255, variation uab d b. dim ensions are in m illim eters. c. dimensions and tolerances per asme y14.5m, 1994. d. draw ing filenam e: m kt-m ac10arev4. 0.10 c 0.10 c 0.10 cab 0.05 c pin1 ident is longer than other lines a b c 0.35 0.25 9x 9x 0.35 0.25 (0.20) (0.15) 0.35 0.25 14 9 6 0.25 0.15 10 5 0.50 0.56 (0.81) (0.25) 1.62 0.05 0.00 0.05 c 0.55 max 0.05 c 1.60 2.10 (0.35) (0.25) 0.50 10 10x (0.11) (0.56) (1.12) (1.62)
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 9 physical dimensions (continued) figure 14. 14-lead thin shrink small outl ine package (tssop), jedec mo-153, 4.4mm wide package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & bottom 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standa rd: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters
fsa2257 ? low r on low-voltage dual spdt bi -directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 10 physical dimensions (continued) figure 15. 10-lead molded small outl ine package (msop), jedec mo-187, 3.0m package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . note: click here for tape and reel specifcations, available at: http://www.fairchildsemi.com/products/analog/pdf/msop10_tr.pdf
fsa2257? low r on low-voltage dual spdt bi-directional analog switch ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fsa2257 rev. 1.0.5 11

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